In semiconductor devices, level shifters are generally used to interface voltage signals between diversely different circuits that operate at different power voltages from each other. For example, a word line driver of a semiconductor device may operate at a high voltage which is higher than an external voltage applied to the semiconductor device. As such, a signal for operating the word line driver may function in a voltage swing range between the external voltage and the ground voltage, and in contrast, the word line driver may need to function at a considerably different voltage swing range between the high voltage and the ground voltage. As a result, if a circuit generating a signal for operating the word line driver, which uses the external voltage lower than the high voltage, is directly coupled to the word line driver, then a leakage current may flow from the word line driver of the high voltage into the circuit of the external voltage. Therefore, level shifters are often times found to be desirable or even deemed necessary for interfacing voltage signals between the two divergent circuits that are different each other with regards to power voltage level requirements.
FIG. 1 shows a circuit of a general level shifter employed in a semiconductor device.
As shown in FIG. 1, the level shifter receives an input signal IN that is at a relatively low voltage, and subsequently generates an output signal OUT that is at a relatively high voltage. An operation of the level shifter is as follows.
First, the case that the input signal IN drops down to the ground voltage VSS from a level V1 will be explained. When the input signal IN is set at a voltage level V1, the output signal OUT is generated at a voltage level V2 as NMOS and PMOS transistors N10 and P11 are turned on by the input signal IN. From this state, if the input signal IN drops down to the ground voltage VSS, an NMOS transistor N11 is turned on. The turn-on state of the PMOS transistor P11 is maintained until a PMOS transistor P10 is turned on to be pulled-up. That is, while the input signal IN is transitioning toward the ground voltage VSS from the voltage level V1, there is a time period in which the NMOS transistor N11 and the PMOS transistor P11 are both turned on concurrently. To prevent this effect, the NMOS transistor N10 is usually designed to be larger in size to enhance a turn-off rate of the PMOS transistor P11.
However, as the level shifter shown in FIG. 1 is being turned on at all times, regardless of whatever the semiconductor device is conditioned in an active mode or a standby mode, a leakage current necessarily continuously flows through the level shifter.